vu cs302 Final Term - Quiz No.10
vu cs302 Digital Logic Design Quiz
This quiz belongs to book/course code vu cs302 Digital Logic Design of vu organization. We have 30 quizzes available related to the book/course Digital Logic Design. This quiz has a total of 10 multiple choice questions (MCQs) to prepare and belongs to topic Final Term. NVAEducation wants its users to help them learn in an easy way. For that purpose, you are free to prepare online MCQs and quizzes.
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Question 3: In memory write cycle, the time for which the WE signal remains active is known as the __________.
Write address setup
Write pulse width
Write delay width
Write data time
Question 5: 74HC163 has two enable input pins which are __________ and __________.
ENP, ENT
ENI, ENC
ENP, ENC
ENT, ENI
Question 6: The output of an XOR gate is zero (0) when __________
I) All the inputs are zero
II) Any of the inputs is zero
III) Any of the inputs is one
IV) All the inputs are one.
I) All the inputs are zero
II) Any of the inputs is zero
III) Any of the inputs is one
IV) All the inputs are one.
I Only
IV Only
I and IV only
II and III only
Question 7: A GAL is essentially a __________.
NonJreprogrammable PAL
PAL that is programmed only by the manufacturer
Very large PAL
Reprogrammable PAL
Question 9: When both the inputs of edge triggered J-K flip-flop are set to logic zero __________
the flip-flop triggered
Q=0, and Q'=1
Q=1and Q'=1
the output of flip flop remains unchanged
Question 10: A positive edge-triggered flip-flop changes its state when __________
Low-to-high transition of clock
High-to-low transition of clock
Enable input (EN) is set
Preset input (PRE) is set
