vu cs302 Final Term - Quiz No.5
vu cs302 Digital Logic Design Quiz
This quiz belongs to book/course code vu cs302 Digital Logic Design of vu organization. We have 30 quizzes available related to the book/course Digital Logic Design. This quiz has a total of 10 multiple choice questions (MCQs) to prepare and belongs to topic Final Term. NVAEducation wants its users to help them learn in an easy way. For that purpose, you are free to prepare online MCQs and quizzes.
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Question 1: The output of an XNOR gate is 1 when __________
I) All the inputs are zero
II) Any of the inputs is zero
III) Any of the inputs is one
IV) All the inputs are one
I) All the inputs are zero
II) Any of the inputs is zero
III) Any of the inputs is one
IV) All the inputs are one
I Only
IV Only
I and IV only
II and III only
Question 2: In NAND based S-R latch, output of each __________ gate is connected to the input of the other __________ gate.
NOR, NAND
NAND, NOR
NOR, NOR
NAND, NAND
Question 3: If the FIFO memory output is ready filled with data then __________
it is locked,no data is allowed to enter
it is not locked,the new data overwrites the previous data
previous data is swapped out of memory and new data enters
none of given
Question 5: Implementation of the FIFO buffer in __________ is usually takes the form of a circular buffer.
RAM
ROM
PPROM
Flash Memory
Question 6: Divide-by-32 counter can be achieved by using
Flip-Flop and DIV 10
Flip-Flop and DIV 16
Flip-Flop and DIV 32
DIV 16 and DIV 32
Question 10: __________ is used to minimize the possible no. of states of a circuit.
State assignment
State reduction
Next state table
State diagram
