vu cs302 Final Term - Quiz No.7
vu cs302 Digital Logic Design Quiz
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Question 3: We have a gidital circuit, different parts of circuit operate at different clock frequencies(4MHZ,2MHZ and1 MHZ) but we have a single clock source having a fix clock frequency(4MHZ), we can get help by __________
using S-R flip-flop
D-flip flop
J-K flip flop
T flip flop
Question 4: __________ counters as the name indicates are not triggered simultaneously.
Asynchronous
Synchronous
Positive-Edge triggered
Negative-Edge triggered
Question 7: __________ is used to minimize the possible no.of state of a circuit
state assignment
state reproduction
next state table
state diagram
Question 8: The domain of the expression AB'CD + AB' + C'D + B is
A and D
B only
A, B, C and D
None of the given
Question 9: A multiplexer with a register circuit converts __________
serial data to parallel
parallel data to serial
serial data to serial
parallel data to parallel
Question 10: An alternative method of implementing comparators which allows the comparators to be easily cascaded without the need for extra logic gates is __________
using a single comparator
using Iterative circuit based comparator
connecting comparators in vertical hierarchy
extra logic gates are always required
