When both the inputs of edge triggered J-K flip-flop are set to-03793
When both the inputs of edge triggered J-K flip-flop are set to logic zero __________
This multiple choice question (MCQ) is related to the book/course
vu cs302 Digital Logic Design.
It can also be found in
vu cs302 Final Term - Quiz No.10.
When both the inputs of edge triggered J-K flip-flop are set to logic zero __________
the flip-flop triggered
Q=0, and Q'=1
Q=1and Q'=1
the output of flip flop remains unchanged
