vu cs302 Final Term - Quiz No.14
vu cs302 Digital Logic Design Quiz
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Question 2: __________ occurs when the same clock signal arries at different times at different clock inputs due to propagation delay
race condition
clock skew
ripple effect
none of given options
Question 3: A transparent mode means __________.
The changes in the data at the inputs of the latch are seen at the output
The changes in the data at the inputs of the latch are not seen at the output
Propagation Delay is zero (Output is immediately changed when clock signal is applied)
Input Hold time is zero (no need to maintain input after clock transition)
