vu cs302 Final Term - Quiz No.11
vu cs302 Digital Logic Design Quiz
This quiz belongs to book/course code vu cs302 Digital Logic Design of vu organization. We have 30 quizzes available related to the book/course Digital Logic Design. This quiz has a total of 10 multiple choice questions (MCQs) to prepare and belongs to topic Final Term. NVAEducation wants its users to help them learn in an easy way. For that purpose, you are free to prepare online MCQs and quizzes.
NVAEducation also facilitates users to contribute in online competitions with other students to make a challenging situation to learn in a creative way. You can create one to one, and group competition on an topic of a book/course code. Also on NVAEducation you can get certifications by passing the online quiz test.
Question 2: An Asynchronous Down-counter is implemented (Using J-K flip-flop) by connecting __________.
Q output of all flip-flops to clock input of next flip-flops
Q' output of all flip-flops to clock input of next flip-flops
Q output of all flip-flops to J input of next flip-flops
Q' output of all flip-flops to K input of next flip-flops
Question 3: A logic circuit with an output consists of __________
two AND gates, two OR gates, two inverters
three AND gates, two OR gates, one inverter
two AND gates, one OR gate, two inverters
two AND gates, one OR gate
Question 4: The 64-cell array organized as 8 x 8 cell array is considered
as an 64 byte memory
as a 16 byte memory
as an 8 byte memory
as an 4 byte memory
Question 5: In the following statement
Z PIN 20 ISTYPE "reg.invert";
The keyword "reg.invert" indicates __________
Z PIN 20 ISTYPE "reg.invert";
The keyword "reg.invert" indicates __________
An inverted register input
An inverted register input at pin 20
Active-high Registered Mode output
Active-low Registered Mode output
Question 6: WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO.
THE FLOP-FLOP IS TRIGGERED
Q=0 AND Q'=1
Q=1 AND Q'=0
THE OUTPUT OF FLIP-FLOP REMAINS UNCHANGED
Question 7: Stack is an acronym failed_or __________
FIFO memory
LIFO memory
Flash Memory
Bust Flash Memory
Question 9: A 3-variable karnaugh map has
eight cells
three cells
sixteen cells
four cells
Question 10: A full added has a Cin=0. What are the sum (PRIVATETYPE=PICT;ALT+sigma) and the carry when A=1 and B=1?
=0,count=0
=0,count=1
=1,count=0
=1,count=1
