The divide-by-60 counter in digital clock is implemented by-03924
The divide-by-60 counter in digital clock is implemented by using two cascading counters:
This multiple choice question (MCQ) is related to the book/course
vu cs302 Digital Logic Design.
It can also be found in
vu cs302 Mid Term - Quiz No.10.
The divide-by-60 counter in digital clock is implemented by using two cascading counters:
Mod-6, Mod-10
Mod-50, Mod-10
Mod-10, Mod-50
Mod-50, Mod-6
